JPL Job Openings – FPGA Engineer III

Website JPL

Job Description:

the Radar Science and Engineering Section (334). You will report to the Radar Section Management Team and the Group Supervisor of the Radar Digital Systems Group.

Job Responsibilities:

  • The VERITAS Synthetic Aperture Radar, the first ever spaceborne Single Pass Interferometer with On Board Interferometric Processing, and the first ever Interferometric SAR sent to another planet; currently in early implementation phase.
  • We are seeking an FPGA (Field Programmable Gate Array) Engineer III, responsible for the design and implementation of digital subsystems part of spaceborne and airborne Radar Systems and their EGSE.
  • In this role you will be an essential team member partnering with a group of firmware, hardware, and software engineers in the development of technology maturation projects as well as implementation of spaceborne and airborne Earth Science and Planetary exploration missions that include Radar systems developed at JPL.
  • The INCUS Precipitation Radars, direct successors of RainCube, the first ever radar in a 6U CubeSat which also demonstrated the first ever application of Onboard Pulse Compression processing for a spaceborne weather radar.
  • The INCUS Radars will be the first ever formation of identical radars to be sent in Low Earth Orbit to observe the evolution of storms; currently in formulation phase.

Job Requirements:

  • Experience developing firmware and software for signal processing and telecom applications.
  • Strong knowledge and background in digital signal processing, modulation and demodulation schemes, telemetry encoding and decoding techniques.
  • Effective communication skills, both written and verbal.
  • Analytical and debugging skills.

Qualification & Experience:

  • A Bachelor’s degree in Electrical Engineering or related disciplines with a minimum of 6 years of related experience; or a Master’s degree in similar disciplines with a minimum of 4 years of related experience; or PhD in similar disciplines with a minimum of 2 years of related experience.
  • Experience with ethernet and related networking protocols, UDP, TCP/IP, etc.
  • Experience with Xilinx FPGA design and verification tools.
  • Experience with embedded software, C/C++, Python.
  • Experience using git and github to manage a code base during development.

Job Details:

Company:  JPL

Vacancy Type:  Full Time

Job Location:  Pasadena, CA, US

Application Deadline: N/A

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